This is your role:
- Working on 7nm and 5nm designs with various customers for deployment of Aprisa place and route tools.
- Are you expertised in solving customer’s problems for critical designs to achieve desired performance, area and power targets!
- Responsible to develop flow and methodology for doing placement, CTS and routing. Also, provide training and technical support to customers using Aprisa tools
We don’t need superheroes, just superminds!
- Typically requires minimum of 1-2 years of experience in Physical Design with mainstream P&R tools
- We are looking for someone with hands on experience in Physical Design (floorplan, placement, CTS and routing) and timing closure of complex blocks and/or Full Chip designs.
- Hands-on experience with commercial place & route tools like Synopsys-lCC2, Cadence-Innovus or Aprisa is a must.
- Tapeout experience of 2 or more projects is a must.
- Do you have good understanding of timing, power and area trade-offs?
- Ability to pickup new flows, learn on the job and influence QOR is a must.
- We are looking for an experienced design delivering with multiple voltage islands and top-level floor-planning & chip-assembly is a plus.
- Strong verbal and written communication skills; good presentation skills; good problem solving and debugging skills.
Education:
- BE/B.Tech in Electronics and Communication (E&C) or Electrical or Telecom Engineering.
- ME/M.Tech in VLSI or Microelectronics is a plus.